1. Field
Exemplary implementations of the present invention relate to a memory and a memory system that can reduce the loading of through vias and lines transferring data and reduce the skewness of data inputted to/outputted from a data input/output pad.
2. Description of the Related Art
A memory may include a plurality of cell arrays in which a plurality of memory cells are disposed in an array. One or more of such cell arrays may form a bank. A memory may also include a plurality of data input/output pads to input/output data to/from a bank selected from among a plurality of banks.
FIG. 1 is block diagram illustrating a configuration of a conventional memory.
As shown in FIG. 1, a memory may include a plurality of banks BK1 to BK8, a plurality of data input/output pads PAD1 to PAD8, a data input circuit IN_CIR, and a data output circuit OUT_CIR.
The operation of the conventional memory will be described with reference to FIG. 1.
In the following description, a case where, whenever a command accompanied with input/output of data is inputted, eight pieces of data are inputted to/outputted from each of the plurality of data input/output pads PAD1 to PAD8 will be described (that is to say, whenever a command accompanied with input/output of data is inputted, 64 pieces of data are inputted to/outputted from the memory).
(1) Data Input Operation (Write Operation)
Data DATA is inputted through the plurality data input/output pads PAD1 to PAD8, together with an address ADD and a write command WT accompanied with input of data DATA. In this case, eight pieces of data are serially inputted to each data input/output pad. The 64 pieces of data inputted to the plurality of data input/output pads PAD1 to PAD8 are serial-to-parallel converted in the data input circuit IN_CIR. The 64 pieces are then are loaded on a global bus GIO_BUS to be transferred to a bank, from among the plurality of banks BK1 to BK8, selected by the address. The bank, from among the plurality of banks BK1 to BK8, selected by the address may generate one or more selection signals YI to select memory cells, from among a plurality of memory cells, in which data DATA received through the global bus GIO_BUS is to be stored using the address ADD, and may write the data DATA in the memory cells selected by the selection signals YI.
(2) Data Output Operation (Read Operation)
When the read command RD is applied, then a bank, from among the plurality of banks BK1 to BK8, selected in response to the address ADD may generate a selection signal YI for selecting memory cells, from among a plurality of memory cells, to which data is to be outputted. Data of the memory cells selected by the selection signal YI may be read and loaded on the global bus GIO_BUS. The data on the global bus GIO_BUS may be transferred to the data output circuit OUT_CIR, may be parallel-to-serial converted, and then may be outputted to the outside of the memory through the plurality of data input/output pads PAD1 to PAD8.
In the memory, the plurality of data input/output pads PAD1 to PAD8 are congregated in a specific position (e.g. the pads are congregated in the left portion of the memory in the case of FIG. 1). Therefore, in order to transfer data from the plurality of data input/output pads PAD1 to PAD8 to a bank selected from among the plurality of banks BK1 to BK8, or to transfer data outputted from a selected bank to the plurality of data input/output pads PAD1 to PAD8, the length of the global bus GIO_BUS for transferring data is long and the loading thereof is great.